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| .coveragerc | |
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| .gitignore | |
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| LICENSE | |
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| README.md | |
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| design_explorer/__init__.py | 7 | A 0 mins |
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| design_explorer/apps/__init__.py | 3 | A 0 mins |
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| design_explorer/apps/generate_graph_data.py | 33 | A 1 hr |
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| design_explorer/apps/generate_vhdl_entity.py | 34 | A 0 mins |
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| design_explorer/apps/hierarchy.py | 67 | A 3 hrs |
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| design_explorer/component.py | 24 | A 50 mins |
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| design_explorer/connection.py | 31 | A 35 mins |
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| design_explorer/hdl/__init__.py | 3 | A 0 mins |
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| design_explorer/hdl/component.py | 7 | A 0 mins |
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| design_explorer/hdl/subblock.py | 7 | A 0 mins |
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| design_explorer/hdl/subsystem.py | 10 | A 0 mins |
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| design_explorer/hw/__init__.py | 3 | A 0 mins |
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| design_explorer/hw/cca.py | 10 | A 0 mins |
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| design_explorer/hw/fpga.py | 12 | A 0 mins |
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| design_explorer/hw/part.py | 9 | A 0 mins |
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| design_explorer/interface.py | 29 | A 0 mins |
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| design_explorer/port.py | 13 | A 0 mins |
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| design_explorer/system.py | 32 | A 1 hr |
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| design_explorer/utils.py | 56 | A 0 mins |
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| docs/source/case_study_1/adc4110_1.rst | |
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| docs/source/case_study_1/discretes.rst | |
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| docs/source/case_study_1/fpga.rst | |
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| docs/source/case_study_1/generate_hw_library.rst | |
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| docs/source/case_study_1/generate_system.rst | |
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| docs/source/case_study_1/generate_system/add_components.rst | |
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| docs/source/case_study_1/generate_system/add_connections.rst | |
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| docs/source/case_study_1/generate_system/create_cca.rst | |
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| docs/source/case_study_1/generate_system/define_interfaces_on_fpga.rst | |
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| docs/source/case_study_1/system_level_requirements.rst | |
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| docs/source/conf.py | 36 | A 0 mins |
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| docs/source/connections.rst | |
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