README.md from rggen/rggen-systemverilog

README.md
Summary

Maintainability

Test Coverage

Issues
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# RgGen::SystemVerilog

RgGen::SystemVerilog provides SystemVerilog RTL and UVM register model (UVM RAL) generators for RgGen.

## Installation

During RgGen installation, RgGen::SytemVerilog will also be installed automatically.

```
$ gem install rggen
```

If you want to install RgGen::SytemVerilog only, use the command below:

```
$ gem isntall rggen-systemverilog
```

## Contact

Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:

* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
* [Chat Room](https://gitter.im/rggen/rggen)
* [Mailing List](https://groups.google.com/d/forum/rggen)
* [Mail](mailto:rggen@googlegroups.com)

## Copyright & License

Copyright &copy; 2019-2024 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.

## Code of Conduct

Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](https://github.com/rggen/rggen-systemverilog/blob/master/CODE_OF_CONDUCT.md).