| lib/rggen/builtins/register/type.rb | 233 | B 5 hrs |
|
| lib/rggen/builtins/bit_field/type.rb | 200 | B 5 hrs |
|
| lib/rggen/builtins/register/types/indirect.rb | 145 | A 55 mins |
|
| lib/rggen/input_base/item.rb | 141 | A 35 mins |
|
| lib/rggen/core_components/verilog_utility/variable.rb | 97 | A 30 mins |
|
| lib/rggen/output_base/item.rb | 91 | A 0 mins |
|
| lib/rggen/builtins/register_block/host_ifs/axi4lite.rb | 90 | A 0 mins |
|
| lib/rggen/builtins/register/reg_model.rb | 88 | A 50 mins |
|
| lib/rggen/core_components/code_utility/source_file.rb | 80 | A 0 mins |
|
| lib/rggen/options.rb | 80 | A 55 mins |
|
| lib/rggen/builder/item_store.rb | 78 | A 45 mins |
|
| lib/rggen/core_components/rtl/item.rb | 72 | A 0 mins |
|
| lib/rggen/builder/list_item_entry.rb | 71 | A 35 mins |
|
| lib/rggen/base/hierarchical_accessors.rb | 69 | A 0 mins |
|
| lib/rggen/core_components/verilog_utility/module_definition.rb | 69 | A 0 mins |
|
| lib/rggen/core_components/verilog_utility/identifier.rb | 68 | A 25 mins |
|
| lib/rggen/builtins/register/types/external.rb | 68 | A 0 mins |
|
| lib/rggen/core_components/register_map/generic_map.rb | 68 | A 0 mins |
|
| lib/rggen/core_components/verilog_utility.rb | 67 | A 0 mins |
|
| lib/rggen/output_base/component.rb | 66 | A 0 mins |
|
| lib/rggen/core_components/verilog_utility/local_scope.rb | 63 | A 0 mins |
|
| lib/rggen/base/hierarchical_item_accessors.rb | 63 | A 0 mins |
|
| lib/rggen/core_components/code_utility/code_block.rb | 62 | A 35 mins |
|
| lib/rggen/builtins/register_block/host_ifs/apb.rb | 61 | A 0 mins |
|
| lib/rggen/generator.rb | 57 | A 0 mins |
|
| lib/rggen/builtins/register_block/base_address.rb | 57 | A 1 hr |
|
| lib/rggen/builtins/register/rtl_top.rb | 57 | A 45 mins |
|
| lib/rggen/builder/builder.rb | 57 | A 0 mins |
|
| lib/rggen/builder/category.rb | 55 | A 0 mins |
|
| lib/rggen.rb | 54 | A 0 mins |
|
| lib/rggen/builtins/register/offset_address.rb | 54 | A 1 hr |
|
| lib/rggen/builtins/register_block/host_if.rb | 53 | A 0 mins |
|
| lib/rggen/option_switches.rb | 52 | A 0 mins |
|
| lib/rggen/builtins.rb | 51 | A 0 mins |
|
| lib/rggen/core_components/ral/item.rb | 49 | A 0 mins |
|
| lib/rggen/core_components/c_utility/data_structure_definition.rb | 49 | A 0 mins |
|
| lib/rggen/core_components/verilog_utility/class_definition.rb | 48 | A 0 mins |
|
| lib/rggen/builtins/register_block/address_struct.rb | 48 | A 0 mins |
|
| lib/rggen/core_components/verilog_utility/package_definition.rb | 48 | A 0 mins |
|
| lib/rggen/input_base/component_factory.rb | 48 | A 0 mins |
|
| lib/rggen/core_components.rb | 46 | A 0 mins |
|
| lib/rggen/builtins/register/indirect_index_configurator.rb | 46 | A 0 mins |
|
| lib/rggen/core_components/code_utility.rb | 45 | A 0 mins |
|
| lib/rggen/builder/component_entry.rb | 44 | A 55 mins |
|
| lib/rggen/builtins/bit_field/types/rwl_rwe.rb | 44 | A 0 mins |
|
| lib/rggen/base/component_factory.rb | 43 | A 45 mins |
|
| lib/rggen/core_components/verilog_utility/structure_definition.rb | 43 | A 0 mins |
|
| lib/rggen/builtins/register/uniqueness_validator.rb | 43 | A 1 hr |
|
| lib/rggen/core_extensions/forwardable.rb | 40 | A 25 mins |
|
| lib/rggen/builder/component_store.rb | 38 | A 45 mins |
|