taichi-ishitani/rggen

rggen_bit_field_w01s_w01c #(
  .MODE             (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
  .SET_CLEAR_VALUE  (<%= clear_value %>),
  .WIDTH            (<%= width %>),
  .INITIAL_VALUE    (<%= initial_value %>)
) u_bit_field (
  .clk            (<%= register_block.clock %>),
  .rst_n          (<%= register_block.reset %>),
  .i_set_or_clear (<%= set[loop_variables] %>),
  .bit_field_if   (<%= bit_field_sub_if %>),
  .o_value        (<%= value_out[loop_variables] %>)
);