ci/scan-circuit-mix/scan-bufs_invs_boxes-chain.circuit.stat.ref
Cycle absence check: false
Combined check: false
Circuit analysis:
Component count (mapped + unmapped) - 13 (12 + 1)
Area - 40.0 + 2*TBUF_scan + 2*TINV_scan + 1*[unmapped]
Non-trivial component count (function + blackbox) - 8 (7 + 1)
Trivial gate count (buffer / 0-delay + inverter / 0-delay + const) - 5 (5 / 0 + 0 / 0 + 0)
Driver pin count (combinational + sequential + undefined) - 14 (12 + 0 + 2)
Literal count combinational / sequential (set + reset) - 27 / 0 (0 + 0)
Port count (input + output) - 16 (10 + 6)
Max fanin / fanout - 5 / 5
Fanin distribution [0 / 1 / 2 ...] - 0 / 5 / 3 / 0 / 4 / 1
Fanout distribution [0 / 1 / 2 ...] - 0 / 17 / 3 / 2 / 1 / 1
Isolated components / ports / pins - 0 / 0 / 0