workcraft/workcraft

// Verilog netlist generated by Workcraft 3
module VME (dsr, dsw, ldtack, d, lds, dtack);
    input dsr, dsw, ldtack;
    output d, lds, dtack;
    wire U1_ON, IN_BUBBLE3_ON, IN_BUBBLE5_ON, U7_ON, IN_BUBBLE10_ON, OUT_BUBBLE1_ON, U14_ON, IN_BUBBLE16_ON, IN_BUBBLE18_ON, U20_ON, IN_BUBBLE23_ON, IN_BUBBLE25_ON, IN_BUBBLE28_ON, OUT_BUBBLE2_ON, U31_ON, IN_BUBBLE33_ON, OUT_BUBBLE3_ON, U36_ON;

    NAND3BX1 U1 (.Y(U1_ON), .AN(OUT_BUBBLE3_ON), .B(ldtack), .C(dsr));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE3 (.Y(IN_BUBBLE3_ON), .A(OUT_BUBBLE2_ON));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE5 (.Y(IN_BUBBLE5_ON), .A(ldtack));
    OAI221X1 U7 (.Y(U7_ON), .A0(IN_BUBBLE3_ON), .A1(d), .B0(IN_BUBBLE5_ON), .B1(OUT_BUBBLE3_ON), .C0(dsw));
    NAND2X1 U8 (.Y(d), .A(U7_ON), .B(U1_ON));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE10 (.Y(IN_BUBBLE10_ON), .A(OUT_BUBBLE3_ON));
    INVX1 OUT_BUBBLE1 (.Y(OUT_BUBBLE1_ON), .A(U14_ON));
    OAI221X1 U14 (.Y(U14_ON), .A0(d), .A1(dsr), .B0(dsr), .B1(OUT_BUBBLE2_ON), .C0(IN_BUBBLE10_ON));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE16 (.Y(IN_BUBBLE16_ON), .A(OUT_BUBBLE2_ON));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE18 (.Y(IN_BUBBLE18_ON), .A(dsw));
    OAI31X1 U20 (.Y(U20_ON), .A0(IN_BUBBLE18_ON), .A1(IN_BUBBLE16_ON), .A2(d), .B0(OUT_BUBBLE3_ON));
    C2 U21 (.Q(lds), .A(U20_ON), .B(OUT_BUBBLE1_ON));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE23 (.Y(IN_BUBBLE23_ON), .A(OUT_BUBBLE3_ON));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE25 (.Y(IN_BUBBLE25_ON), .A(OUT_BUBBLE2_ON));
    AOI221X1 U26 (.Y(dtack), .A0(IN_BUBBLE23_ON), .A1(dsw), .B0(d), .B1(OUT_BUBBLE3_ON), .C0(IN_BUBBLE25_ON));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE28 (.Y(IN_BUBBLE28_ON), .A(OUT_BUBBLE3_ON));
    INVX1 OUT_BUBBLE2 (.Y(OUT_BUBBLE2_ON), .A(U31_ON));
    OAI222X1 U31 (.Y(U31_ON), .A0(IN_BUBBLE28_ON), .A1(dsw), .B0(OUT_BUBBLE2_ON), .B1(d), .C0(d), .C1(lds));
    // This inverter should have a short delay
    INVX1 IN_BUBBLE33 (.Y(IN_BUBBLE33_ON), .A(d));
    INVX1 OUT_BUBBLE3 (.Y(OUT_BUBBLE3_ON), .A(U36_ON));
    AOI32X1 U36 (.Y(U36_ON), .A0(IN_BUBBLE33_ON), .A1(ldtack), .A2(OUT_BUBBLE2_ON), .B0(ldtack), .B1(OUT_BUBBLE3_ON));

    // signal values at the initial state:
    // IN_BUBBLE10_ON IN_BUBBLE16_ON IN_BUBBLE18_ON IN_BUBBLE23_ON IN_BUBBLE25_ON IN_BUBBLE28_ON IN_BUBBLE33_ON IN_BUBBLE3_ON IN_BUBBLE5_ON !OUT_BUBBLE1_ON !OUT_BUBBLE2_ON !OUT_BUBBLE3_ON U14_ON U1_ON U20_ON U31_ON U36_ON U7_ON !d !dsr !dsw !dtack !lds !ldtack
endmodule