ci/synthesis-atacs/atacs-vme-stdc.circuit.stat.ref
Circuit analysis:
Component count (mapped + unmapped) - 18 (0 + 18)
Area - 0.0 + 18*[unmapped]
Non-trivial component count (function + blackbox) - 14 (14 + 0)
Trivial gate count (buffer / 0-delay + inverter / 0-delay + const) - 4 (3 / 0 + 1 / 0 + 0)
Driver pin count (combinational + sequential + undefined) - 18 (15 + 3 + 0)
Literal count combinational / sequential (set + reset) - 30 / 12 (6 + 6)
Port count (input + output) - 6 (3 + 3)
Isolated components / ports / pins - 0 / 0 / 0